1. Field
Exemplary embodiments of the present invention relate to a memory device.
2. Description of the Related Art
Memory devices have a plurality of memory cells for storing data. Each memory cell may include a MOS transistor functioning as a switch and a capacitor for storing a charge representing data stored in the memory cell. For example, a charge stored in a capacitor may represent a ‘1’ or a ‘0’ in a binary logic system depending upon whether the stored charge is high or low.
Ideally, no consumption of power is needed to retain data stored in a memory cell. However, in practice, the stored data may not be retained for a long time period because a charge initially stored in a capacitor of a memory cell may be lost due to a leakage current occurring at the PN junction of a MOS transistor. Before stored data is lost, for preventing data loss, stored data are read and the charges corresponding to the read data are recharged into the memory cells. Such a process is known as a refresh operation and is typically repeated periodically for maintaining the integrity of stored data.
FIG. 1 is a diagram showing part of a cell array included in a memory device. In FIG. 1, “BL” denotes a bit line.
In the cell array of FIG. 1, WLK−1, WLK (HIGH_ACT), and WLK+1 denote three word lines disposed in parallel to one another. The word line WLK(HIGH_ACT) is a word line having a larger activation number or higher activation frequency than the other word lines. The word line WLK−1 and the word line WLK+1 are disposed adjacent on either side of the word line WLK. CELL_K−1, CELL_K, and CELL_K+1 are memory cells coupled to the word lines WLK−1, WLK (HIGH_ACT), and WLK+1, respectively. The memory cells CELL_K−1, CELL_K, and CELL_K+1 include respective cell transistors TR_K−1, TR_K, and TR_K+1 and respective cell capacitors CAP_K−1, CAP_K, and CAP_K+1.
In FIG. 1, when the word line WLK (HIGH_ACT) is activated or precharged (or deactivated), the voltages of the word line WLK−1 and the word line WLK+1 may rise and fall due to a coupling phenomenon generated between the word line WLK (HIGH_ACT) and each of the word lines WLK−1 and WLK+1, which also affects the charges stored in their respective cell capacitors CAP_K−1 and CAP_K+1. Accordingly, if the word line WLK (HIGH_ACT) is activated and precharged frequently, that is, if the word line WLK (HIGH_ACT) is toggled in the active, precharge state, data stored in the cell capacitors CELL_K−1 and CELL_K+1 may be damaged due to a change in the charges stored in the cell capacitors CAP_K−1 and CAP_K+1. This is often referred to as a row hammer phenomenon.
Furthermore, the data of the memory cells may be damaged due to electromagnetic waves generated when the word line WLK (HIGH_ACT) is toggled in the active, precharge state which may drain electrons from the cell capacitors CAP_K−1 and CAP_K+1.